Page 51 – Numerical Problems (5-Level CHB Inverter)

Subject: Power Electronics
Level: GATE / PSU Advanced Numericals

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🔹 Problem 1 – Number of Levels

A cascaded H-bridge inverter uses 3 identical H-bridge cells per phase. Find number of output voltage levels.

Formula: Levels = 2n + 1

n = 3 Levels = 2(3) + 1 = 7

Final Answer: 7 levels

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🔹 Problem 2 – Maximum Output Voltage

A 5-level CHB inverter uses two DC sources of 200 V each. Find maximum output voltage.

Maximum output = +2Vdc = 200 + 200 = 400 V

Final Answer: 400 V

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🔹 Problem 3 – Voltage Steps

For a 5-level inverter with Vdc = 250 V, list all output voltage levels.

+2Vdc = +500 V +Vdc = +250 V 0 −250 V −500 V

Answer: +500, +250, 0, −250, −500 V

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🔹 Problem 4 – Total Number of Switches

Each H-bridge uses 4 switches. For a 5-level CHB inverter (2 H-bridges per phase), find total switches per phase.

Switches per H-bridge = 4 Total = 2 × 4 = 8 switches per phase

Final Answer: 8 switches per phase

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🔹 Problem 5 – 3-Phase System Switch Count

For a 3-phase 5-level CHB inverter, find total number of switches.

Per phase = 8 switches 3 phases → 3 × 8 = 24 switches

Final Answer: 24 switches

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🔹 Problem 6 – THD Concept

If number of levels increases from 5 to 7, what happens to THD?

More levels → waveform closer to sine → THD decreases.

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🔹 Problem 7 – Required DC Sources

A 9-level CHB inverter is required. Find number of H-bridge cells per phase.

Levels = 2n + 1

9 = 2n + 1 2n = 8 n = 4

Final Answer: 4 H-bridges per phase

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 Exam Memory Section

✔ Levels = 2n + 1 ✔ Switches per phase = 4n ✔ More levels → Lower THD ✔ 5-level → 2 DC sources ✔ 7-level → 3 DC sources

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Multilevel Inverter Numerical Series – Shaktimatha Learning

 

Page 50 – 5-Level Cascaded H-Bridge Inverter (Detailed Operation)

Subject: Power Electronics
Level: GATE / PSU / Interview Advanced

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🔹 1. Basic Concept

A 5-level inverter can be built using 2 H-bridge cells connected in series.

Using formula: Levels = 2n + 1 n = 2 → Levels = 5

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🔹 2. Output Voltage Levels

Possible output voltages: +2Vdc +Vdc 0 −Vdc −2Vdc

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🔹 3. Switching Combinations

Each H-bridge can produce:

• +Vdc
• 0
• −Vdc

By combining two bridges: (+Vdc + +Vdc) = +2Vdc (+Vdc + 0) = +Vdc (+Vdc + −Vdc) = 0 (0 + −Vdc) = −Vdc (−Vdc + −Vdc) = −2Vdc

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🔹 4. Advantages of 5-Level CHB

• Better waveform quality
• Reduced THD
• Lower filter requirement
• Suitable for medium voltage drives

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🔹 5. Harmonic Reduction

More levels → waveform closer to sine → Lower THD → smaller filter → better efficiency.

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🔹 6. Applications

• Renewable energy systems
• Solar inverters
• HVDC systems
• FACTS devices
• Medium voltage motor drives

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 Important Exam Points

✔ Levels = 2n + 1 ✔ 2 H-bridges → 5 levels ✔ THD decreases with more levels ✔ Requires isolated DC sources ✔ High voltage capability

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Multilevel Inverter Series – Shaktimatha Learning

 

Page 49 – Multilevel Inverter (MLI) – Introduction

Subject: Power Electronics
Level: GATE / PSU / Interview

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🔹 1. What is a Multilevel Inverter?

A multilevel inverter produces output voltage with multiple discrete levels instead of only two levels (+Vdc and −Vdc).

Instead of square waveform → staircase waveform → closer to sine wave.

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🔹 2. Why Multilevel Inverters?

• Lower harmonic distortion (THD)
• Reduced switching losses
• Lower dv/dt stress
• Better output waveform quality
• Suitable for high voltage applications

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🔹 3. Types of Multilevel Inverters

1️⃣ Diode Clamped (Neutral Point Clamped - NPC)

Uses clamping diodes to achieve multiple voltage levels.

2️⃣ Flying Capacitor (Capacitor Clamped)

Uses capacitors to generate intermediate voltage levels.

3️⃣ Cascaded H-Bridge (CHB)

Uses multiple H-bridge cells with isolated DC sources.

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🔹 4. Number of Output Levels

For Cascaded H-Bridge: Number of levels = 2n + 1 Where n = number of H-bridge cells

Example: n = 2 → Levels = 5 n = 3 → Levels = 7

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🔹 5. Advantages

• Low THD
• Reduced filter requirement
• Suitable for HVDC & FACTS
• High power applications

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🔹 6. Disadvantages

• More components
• Complex control
• Voltage balancing issues

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 Exam Important Formula

CHB Levels = 2n + 1 NPC Diodes = (m − 1)(m − 2) Switch count increases with level

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Multilevel Inverter Series – Shaktimatha Learning

 

Page 48 – Ultra Hard Multi-Step Problems

Subject: Power Electronics
Level: GATE / PSU Ultra Advanced

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🔹 Problem 1 – Combined SPWM + Frequency + Voltage

A 3-phase inverter has Vdc = 750 V. Modulation index mₐ = 0.85. Switching frequency = 12 kHz. Fundamental frequency = 50 Hz. Find: 1) Maximum line voltage 2) Switching period 3) Frequency ratio mf

Step 1: Line voltage (SPWM) VLL = 0.866 × mₐ × Vdc = 0.866 × 0.85 × 750 = 552 V

Step 2: Switching period Ts = 1 / fs = 1 / 12000 = 83.3 μs

Step 3: Frequency ratio mf = fs / f = 12000 / 50 = 240

Final Answers: VLL ≈ 552 V Ts ≈ 83 μs mf = 240

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🔹 Problem 2 – SVPWM Sector + Switching Times

Vdc = 600 V Ts = 100 μs Reference voltage = 400 V Angle α = 35° Find sector and T₁, T₂ (approx).

Sector width = 60° 35° lies in Sector 1

T₁ = Ts (Vref/Vdc) sin(60° − α) T₂ = Ts (Vref/Vdc) sin(α)

Vref/Vdc = 400/600 = 0.667 T₁ ≈ 100 × 0.667 × sin(25°) ≈ 100 × 0.667 × 0.422 ≈ 28 μs T₂ ≈ 100 × 0.667 × sin(35°) ≈ 100 × 0.667 × 0.574 ≈ 38 μs

T₀ = 100 − (28 + 38) = 34 μs

Final: Sector 1, T₁ ≈ 28 μs, T₂ ≈ 38 μs, T₀ ≈ 34 μs

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🔹 Problem 3 – Overmodulation Decision + THD Concept

Vdc = 650 V Required line voltage = 600 V Check if SPWM works.

SPWM max = 0.866 × 650 = 563 V Required = 600 V > 563 V → SPWM cannot achieve → Overmodulation needed → THD increases

Conclusion: Operates in overmodulation region.

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🔹 Problem 4 – Multi-Concept Trap (Phase + Line)

Vdc = 500 V mₐ = 0.9 Find: 1) Phase voltage 2) Line voltage

Phase voltage Vphase = mₐ × Vdc / 2 = 0.9 × 500 / 2 = 225 V

Line voltage VLL = √3 × Vphase = 1.732 × 225 ≈ 390 V

Final: Vphase = 225 V, VLL ≈ 390 V

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 Ultra Exam Memory Zone

✔ SPWM → 0.866 Vdc ✔ SVPWM → Vdc ✔ mf = fs / f ✔ T₀ = Ts − (T₁ + T₂) ✔ Overmodulation → Higher THD ✔ Sector width = 60°

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Ultra Advanced Practice Series – Shaktimatha Learning

 

Page 47 – Very Hard Numerical Problems

Subject: Power Electronics
Level: GATE / PSU Advanced Numericals

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🔹 Problem 1 – SPWM Fundamental Voltage

A 3-phase inverter operates with Vdc = 700 V and modulation index mₐ = 0.9. Find maximum fundamental line voltage.

VLL = 0.866 × mₐ × Vdc

= 0.866 × 0.9 × 700
= 0.866 × 630
= 545.6 V

Final Answer: 546 V

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🔹 Problem 2 – SVPWM Switching Times

Switching period Ts = 100 μs. If T₁ = 35 μs and T₂ = 25 μs, find zero vector time.

T₀ = Ts − (T₁ + T₂)

= 100 − (35 + 25)
= 100 − 60
= 40 μs

Final Answer: 40 μs

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🔹 Problem 3 – Overmodulation Region

For Vdc = 600 V and required line voltage = 580 V, determine if SPWM can achieve this.

Max SPWM line voltage = 0.866 × 600 = 519.6 V
Required = 580 V > 519.6 V
Hence SPWM cannot achieve → Overmodulation required.

Conclusion: Overmodulation region

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🔹 Problem 4 – Switching Frequency Calculation

If switching period Ts = 50 μs, find switching frequency.

fs = 1 / Ts
= 1 / (50 × 10⁻⁶)
= 20 kHz

Final Answer: 20 kHz

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🔹 Problem 5 – Harmonic Reduction

Switching frequency increased from 5 kHz to 15 kHz. Comment on harmonic performance.

Higher switching frequency → Harmonics shift to higher frequency → Easier filtering → Lower THD.

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🔹 Problem 6 – Sector Identification

Reference angle α = 275°. Identify sector.

Each sector = 60°
240°–300° = Sector 5
275° lies in Sector 5.

Answer: Sector 5

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🔹 Problem 7 – Phase Voltage

For Vdc = 500 V and mₐ = 0.8, find fundamental phase voltage.

Vphase = mₐ × Vdc / 2

= 0.8 × 500 / 2
= 400 / 2
= 200 V

Final Answer: 200 V

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🔹 Problem 8 – DC Bus Utilization Comparison

Vdc = 800 V. Compare SPWM and SVPWM maximum line voltages.

SPWM max = 0.866 × 800 = 692.8 V
SVPWM max = 800 V
Improvement ≈ 107.2 V

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 Exam Memory Points

✔ SPWM max = 0.866 Vdc
✔ SVPWM max = Vdc
✔ T₀ = Ts − (T₁ + T₂)
✔ fs = 1/Ts
✔ Sector width = 60°

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Advanced Numerical Series – Shaktimatha Learning

 

Page 46 – Very Tough Mixed MCQ Test

Subject: Power Electronics
Level: GATE / PSU Advanced

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Q1.

In SPWM, linear modulation region exists for: A) mₐ > 1 B) mₐ < 1 C) mₐ = 2 D) mₐ = 0

Answer: B

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Q2.

Maximum line voltage in SVPWM equals: A) 0.866 Vdc B) 0.707 Vdc C) Vdc D) 1.2 Vdc

Answer: C

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Q3.

Total active vectors in a 3-phase inverter: A) 8 B) 6 C) 4 D) 2

Answer: B

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Q4.

If switching frequency = 10 kHz, switching period Ts equals: A) 0.1 ms B) 1 ms C) 10 ms D) 100 μs

Answer: D

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Q5.

If Vdc = 500V, find max fundamental line voltage in SPWM.

VLL = 0.866 × 500 = 433 V

Answer: 433 V

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Q6.

Number of sectors in SVPWM: A) 4 B) 6 C) 8 D) 12

Answer: B

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Q7.

Shoot-through condition occurs when: A) Zero vectors applied B) Both switches of same leg ON C) Dead-time inserted D) Reference vector zero

Answer: B

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Q8.

Improvement of SVPWM over SPWM is approximately: A) 5% B) 10% C) 15% D) 20%

Answer: C

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Q9.

If α = 150°, the vector lies in: A) Sector 1 B) Sector 2 C) Sector 3 D) Sector 4

Answer: C

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Q10.

In 120° conduction mode, number of conducting switches: A) 3 B) 2 C) 6 D) 1

Answer: B

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Q11.

Vdc = 600V. SVPWM max line voltage equals:

Answer: 600 V

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Q12.

Total switching states:

Answer: 8

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Q13.

Fundamental phase voltage in SPWM:

Answer: mₐ × Vdc / 2

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Q14.

Dead-time is introduced to:

Answer: Prevent shoot-through

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Q15.

Switching frequency affects: A) Output frequency B) Harmonics C) DC link voltage D) Load power factor

Answer: B

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Q16.

If mₐ = 1.2, operation is:

Answer: Overmodulation

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Q17.

Zero vectors are:

Answer: (000) and (111)

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Q18.

Ts = 100 μs. If T₁ + T₂ = 70 μs, find T₀:

Answer: 30 μs

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Q19.

In 180° mode, each switch conducts for:

Answer: 180°

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Q20.

Maximum theoretical DC utilization in SPWM:

Answer: 86.6%

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Q21–25.

• Sector angle width = 60°
• Reference vector rotates at fundamental frequency
• Carrier frequency >> fundamental frequency
• THD reduces when switching frequency increases
• SVPWM reduces harmonic distortion compared to SPWM

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 Exam Strategy Tip

✔ Memorize 0.866 Vdc (SPWM)
✔ SVPWM = Vdc
✔ 8 states → 6 active + 2 zero
✔ 6 sectors → 60° each
✔ T₀ = Ts − (T₁ + T₂)

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Advanced Power Electronics Practice – Shaktimatha Learning

 

Page 45 – Multiple Questions with Explanation

Subject: Power Electronics
Level: GATE / PSU Concept + Numerical Practice

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🔹 Q1. In SPWM, maximum fundamental line voltage is:

A) Vdc
B) 0.5 Vdc
C) 0.866 Vdc
D) 1.2 Vdc

Correct Answer: C) 0.866 Vdc

Explanation:
In SPWM, modulation index mₐ ≤ 1 in linear region. Maximum achievable line voltage = √3/2 × Vdc ≈ 0.866 Vdc.

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🔹 Q2. SVPWM improves DC bus utilization by approximately:

A) 5%
B) 10%
C) 15%
D) 25%

Correct Answer: C) 15%

Explanation:
SPWM max = 0.866 Vdc
SVPWM max = Vdc
Improvement ≈ (1 − 0.866)/0.866 ≈ 15%.

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🔹 Q3. A three-phase inverter has how many switching states?

A) 6
B) 8
C) 4
D) 12

Correct Answer: B) 8

Explanation:
3 legs → each leg has 2 states.
Total states = 2³ = 8.
6 active vectors + 2 zero vectors.

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🔹 Q4. If α = 75°, the reference vector lies in:

A) Sector 1
B) Sector 2
C) Sector 3
D) Sector 4

Correct Answer: B) Sector 2

Explanation:
Each sector = 60°.
Sector 1 → 0°–60°
Sector 2 → 60°–120°
75° lies in Sector 2.

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🔹 Q5. If Vdc = 600 V and mₐ = 0.8 (SPWM), find fundamental line voltage.

VLL = 0.866 × mₐ × Vdc

= 0.866 × 0.8 × 600
= 0.866 × 480
≈ 415.7 V

Final Answer: ≈ 416 V

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🔹 Q6. Why must upper and lower switches of same leg never be ON together?

Correct Answer: Shoot-through fault.

Explanation:
It directly short-circuits the DC supply, causing large current and device damage. Dead-time is introduced to avoid this.

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🔹 Q7. In 180° conduction mode, how many switches conduct simultaneously?

A) 1
B) 2
C) 3
D) 6

Correct Answer: C) 3

Explanation:
In 180° mode, each switch conducts for 180°.
At any instant, 3 switches are ON.

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 Quick Exam Reminder

✔ SPWM → 0.866 Vdc
✔ SVPWM → Vdc
✔ 6 sectors (60° each)
✔ 8 switching states
✔ Avoid shoot-through fault

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Power Electronics Exam Series – Shaktimatha Learning