Saturday, 28 February 2026

GATE Electrical – Analog Electronics Complete Structured Course

High Weightage Subject for GATE / PSU / Interviews Concept + Derivations + Small Signal Models + Numerical Problems

🔹 Subject Importance in GATE

✔ Weightage: 8–12 Marks ✔ Concept + Numerical Heavy ✔ Requires strong fundamentals ✔ Direct scoring subject if well prepared

🔹 Complete Syllabus Coverage Plan

1️⃣ Diodes

PN Junction Theory
V-I Characteristics
Zener Diode
Rectifiers
Clipper & Clamper
Small Signal Model
Numerical Problems

2️⃣ BJT

BJT Operation (CE, CB, CC)
Biasing Techniques
Stability Factor
Hybrid-π Model
CE Amplifier Gain Derivation
Frequency Response
Miller Effect
Numerical Problems

3️⃣ MOSFET

Regions of Operation
Biasing
Small Signal Model
Common Source Amplifier
Gain & Frequency Response

4️⃣ Differential & Multistage Amplifiers

Differential Amplifier
CMRR
Darlington Pair
Cascaded Amplifiers

5️⃣ Feedback & Stability

Types of Feedback
Gain with Feedback
Bandwidth Effect
Stability Analysis

6️⃣ Operational Amplifiers

Ideal vs Practical Op-Amp
Inverting / Non-Inverting
Integrator & Differentiator
Instrumentation Amplifier
Active Filters

7️⃣ Oscillators

Barkhausen Criterion
RC Phase Shift
Wien Bridge
LC Oscillators

🔹 Learning Strategy

✔ First understand device physics ✔ Then small signal model ✔ Then derive gain equations ✔ Then solve numerical problems ✔ Finally attempt GATE-level MCQs

Analog Electronics – Complete Structured Preparation | Shaktimatha Learning

Friday, 27 February 2026

📘 GATE Electrical Power Systems – Complete Structured Course (2026) | Click Here

GATE Electrical – Power Electronics Complete Mega Master Library (2026)

Complete Theory + Derivations + Waveforms + Numerical Problems + Ultra Hard Practice + PYQ + Mock Tests For GATE / PSU / Interviews – Structured Learning

🔹 1️⃣ Power Diode & Uncontrolled Rectifiers

🔹 2️⃣ Controlled Rectifiers (SCR Based)

🔹 3️⃣ Fully Controlled Bridge & Dual Converters

🔹 4️⃣ Three Phase Converters

🔹 5️⃣ DC-DC Converters (Choppers)

🔹 6️⃣ Inverters & PWM

🔹 7️⃣ Multilevel Inverters

🔹 8️⃣ Mega Practice & Tests

This is the COMPLETE Power Electronics Preparation Library Structured from Basics → Advanced → Ultra Hard → Final Revision

Shaktimatha Learning – Power Electronics Master Library 2026

POWER ELECTRONICS – PAGE 19

Fully Controlled Bridge – Inverter Mode

1️⃣ When Does Inverter Mode Occur?

When α > 90°

Average voltage becomes negative
Power flows from DC to AC side

2️⃣ Condition for Inverter Operation

Load must have DC source (like battery)
SCR firing angle between 90° and 180°

3️⃣ Average Voltage

Vavg = (2Vm / π) cos α

Since cos α becomes negative → Vavg negative.

4️⃣ Power Flow Direction

Rectifier Mode → AC to DC
Inverter Mode → DC to AC

🎯 GATE Important

Understand sign of cos α
Power reversal concept
Waveform identification

Very Important: Fully controlled bridge is reversible converter.

Page 70 – Complete Power Electronics Formula Sheet

For GATE / PSU / Interviews – Final Revision

🔹 1️⃣ Controlled Rectifiers

Single Phase Full Converter: Vo = (2Vm/π) cosα

Half Controlled Converter: Vo = (Vm/π)(1 + cosα)

Inversion mode: α > 90°

🔹 2️⃣ DC-DC Converters (CCM)

Buck: Vo = D Vin

Boost: Vo = Vin / (1 − D)

Buck-Boost: Vo = − D Vin / (1 − D)

SEPIC: Vo/Vin = D / (1 − D)

Ćuk: Vo/Vin = − D / (1 − D)

🔹 3️⃣ DCM Gain (Buck-Boost)

Vo/Vin = − (D² R) / (2Lfs)

🔹 4️⃣ Ripple Equations

Inductor Ripple: ΔIL = Vin D / (L fs)

Output Voltage Ripple (Buck): ΔVo = ΔIL / (8Cfs)

🔹 5️⃣ Critical Inductance

Lcritical = R(1 − D)² / (2fs)

🔹 6️⃣ Inverters

Square Wave Fundamental RMS: V1(rms) = (4Vdc) / (π√2)

THD decreases as switching frequency increases

🔹 7️⃣ LC Filter & Control

Natural Frequency: ω₀ = 1 / √(LC)

Quality Factor: Q = R √(C/L)

ESR Zero: ωz = 1 / (RESR × C)

🔹 8️⃣ Device Formulas

MOSFET Conduction Loss: P = I²Rds(on)

Inductor Energy: E = ½ L I²

Capacitor Energy: E = ½ C V²

🔹 9️⃣ Efficiency

η = Pout / Pin

For boost: Pin = Vin × Iin Pout = Vo × Io

Final Exam Checklist

✔ Always check CCM/DCM ✔ Remember polarity of Buck-Boost ✔ Inversion when α > 90° ✔ Natural frequency from LC ✔ Switching frequency reduces ripple ✔ MOSFET → high frequency ✔ IGBT → high voltage

Complete Power Electronics Final Revision – Shaktimatha Learning

Page 70 – Full Length GATE Pattern Mock Test (Power Electronics)

Total Marks: 50
Duration: 45–60 Minutes

🔹 Section A – 1 Mark MCQs (10 × 1 = 10 Marks)

Q1. Buck converter gain is: A) D B) 1/(1−D) C) −D/(1−D) D) 1/D Q2. IGBT is voltage controlled device. (True/False) Q3. Boost converter operates in CCM when inductor current: A) Zero B) Negative C) Never zero D) Sinusoidal Q4. Inversion occurs in full converter when α > ? Q5. Natural frequency of LC circuit equals? Q6. MOSFET is preferred at: A) Low frequency B) High frequency C) High voltage 10kV D) HVDC Q7. Ripple decreases when switching frequency: A) Decreases B) Increases Q8. Buck-Boost polarity: A) Same B) Opposite Q9. ESR introduces: A) Pole B) Zero Q10. DCM gain depends on: A) Only D B) D, R, L, fs

🔹 Section B – 2 Marks Numerical (10 × 2 = 20 Marks)

Q11. Buck converter Vin=24V, D=0.5, R=12Ω Find output power. Q12. Boost converter Vin=20V, D=0.6 Find Vo. Q13. Buck-Boost Vin=30V, D=0.4 Find Vo. Q14. Inductor ripple Vin=40V, D=0.5, L=200µH, fs=50kHz Q15. Critical inductance R=10Ω, D=0.5, fs=25kHz Q16. Rectifier Vm=325V, α=60° Q17. Inverter fundamental RMS Vdc=200V Q18. Natural frequency L=100µH, C=100µF Q19. Energy stored L=150µH, I=6A Q20. MOSFET conduction loss Rds=0.25Ω, I=5A

🔹 Section C – 3 Marks Tough Problems (5 × 3 = 15 Marks)

Q21. Identify CCM/DCM Vin=24V, D=0.6, L=30µH, R=8Ω, fs=50kHz Q22. SEPIC duty range Vin=15–30V, Vo=20V Q23. Boost efficiency 90% Vin=24V, Vo=48V, Io=4A Find input current. Q24. Buck small-signal order & natural frequency L=200µH, C=50µF Q25. Full converter inversion mode Vm=325V, α=120° Find output.

🔹 Answer Key (Brief)

Q1-A Q2-True Q3-C Q4-90° Q5-1/√LC Q6-B Q7-Increases Q8-Opposite Q9-Zero Q10-B Q11-24W Q12-50V Q13-−20V Q14-2A Q15-50µH Q16-103V Q17-180V Q18-10000 rad/s Q19-2.7mJ Q20-6.25W Q21-Compare Lcritical Q22-D=0.4–0.57 Q23-~8.9A Q24-Second order Q25-−103V

Mock Test Strategy

✔ Attempt easy MCQs first ✔ Numerical → check units carefully ✔ Always test CCM/DCM ✔ Keep 5 minutes for review

Power Electronics Full Length Mock – Shaktimatha Learning

Page 69 – Numerical Marathon (Part 2 – Ultra Hard)

Level: GATE / PSU Ultra Hard

🔹 Problem 1 – Mode Identification + Output

Vin = 24V D = 0.5 L = 20µH R = 12Ω fs = 50kHz Find mode and output voltage.

Step 1: Lcritical = R(1−D)²/(2fs) = 12×0.25/(100000) = 3/100000 = 30µH Given L = 20µH < Lcritical → DCM Step 2: DCM Gain Vo/Vin = −(D²R)/(2Lfs) = −(0.25×12)/(2×20×10⁻⁶×50000) = −3/(2) = −1.5 Vo = −36V

---

🔹 Problem 2 – Boost Ripple & Power

Vin=30V D=0.6 L=150µH R=15Ω fs=40kHz

Vo = 30/(1−0.6)=75V Io = 75/15=5A P = 75×5=375W Ripple: ΔIL=VinD/(Lfs) =30×0.6/(150×10⁻⁶×40000) =18/6 =3A

---

🔹 Problem 3 – Rectifier Inversion

Vm=325V α=120°

Vo=(2Vm/π)cosα = (650/3.14)(−0.5) ≈ −103V Negative → Inversion Mode

---

🔹 Problem 4 – Buck Control Frequency

L=100µH C=50µF Find natural frequency.

ω₀=1/√(LC) =1/√(5×10⁻⁹) ≈ 14142 rad/s f₀ ≈ 2250 Hz

---

🔹 Problem 5 – SEPIC Duty Range

Vin varies 18–36V Vo=24V

Vo/Vin=D/(1−D) Case1: 24/18=1.33 D=0.57 Case2: 24/36=0.67 D=0.4 Duty range: 0.4–0.57

---

🔹 Problem 6 – Inverter THD Concept

If switching frequency increases:

Harmonics shift to higher frequency THD reduces Filter size decreases

---

🔹 Problem 7 – Energy Stored

L=200µH I=5A

Energy = ½LI² =0.5×200×10⁻⁶×25 =2.5mJ

---

🔹 Problem 8 – MOSFET Loss

Rds(on)=0.2Ω I=4A

Conduction loss = I²R =16×0.2 =3.2W

---

Ultra Hard Key Learning

✔ Always compare L with Lcritical ✔ DCM can produce large gain ✔ Inversion when α > 90° ✔ Switching frequency affects THD & filter size ✔ Control frequency ≠ switching frequency

Power Electronics Ultra Hard Marathon – Shaktimatha Learning

Page 68 – Numerical Marathon (30 Hard Problems – Part 1)

Level: GATE / PSU Intensive Practice

🔹 Problem 1 – Buck Converter

Vin = 36V D = 0.5 R = 9Ω Find output power.

Vo = D × Vin = 18V Io = 18/9 = 2A P = 18 × 2 = 36W

---

🔹 Problem 2 – Boost Converter

Vin = 12V D = 0.75 R = 24Ω Find output voltage and power.

Vo = 12/(1−0.75) = 48V Io = 48/24 = 2A P = 48 × 2 = 96W

---

🔹 Problem 3 – Buck-Boost

Vin = 20V D = 0.6 R = 10Ω

Vo = −(0.6/0.4)×20 = −30V Io = 30/10 = 3A P = 30 × 3 = 90W

---

🔹 Problem 4 – Inductor Ripple

Vin=24V D=0.4 L=100µH fs=50kHz

ΔIL = VinD/(Lfs) = 24×0.4/(100×10⁻⁶×50000) = 9.6/5 = 1.92A

---

🔹 Problem 5 – Critical Inductance

R=12Ω D=0.5 fs=25kHz

Lcritical = R(1−D)²/(2fs) = 12×0.25/(50000) = 3/50000 = 60µH

---

🔹 Problem 6 – Rectifier

Vm=325V α=30°

Vo=(2Vm/π)cosα = (650/3.14)(0.866) ≈ 179V

---

🔹 Problem 7 – Inverter Fundamental

Vdc=200V

V1(rms)=(4Vdc)/(π√2) ≈ 180V

---

🔹 Problem 8 – Natural Frequency

L=100µH C=25µF

ω₀=1/√(LC) =1/√(2.5×10⁻⁹) ≈ 20000 rad/s

---

🔹 Problem 9 – Boost Duty

Vin=30V Vo=60V

60=30/(1−D) 1−D=0.5 D=0.5

---

🔹 Problem 10 – DCM Output

Vin=20V D=0.4 R=10Ω L=100µH fs=50kHz

Vo/Vin=−(D²R)/(2Lfs) =−(0.16×10)/(10) =−0.16 Vo=−3.2V

---

Marathon Strategy

✔ Always check CCM/DCM ✔ Write gain formula correctly ✔ Keep calculator accuracy ✔ Manage time – 2 min per problem

Power Electronics Numerical Marathon – Shaktimatha Learning

Page 67 – 100 Very Tough MCQs (Part 2 – Advanced Numericals)

Level: GATE / PSU Advanced Numerical

🔹 DC-DC Converters

Q1. A buck converter operates with Vin = 48 V, D = 0.25, R = 12 Ω. Find output power. A) 12 W B) 24 W C) 48 W D) 96 W

Vo = D Vin = 0.25 × 48 = 12 V Io = 12/12 = 1 A P = 12 × 1 = 12 W Answer: A

--- Q2. Boost converter with D = 0.6. Find voltage gain. A) 1.5 B) 2 C) 2.5 D) 3

Gain = 1/(1−D) = 1/0.4 = 2.5 Answer: C

--- Q3. Buck-Boost with D = 0.75. Gain magnitude equals? A) 3 B) 2 C) 1 D) 0.5

|Vo/Vin| = D/(1−D) = 0.75/0.25 = 3 Answer: A

---

🔹 DCM Concept

Q4. In DCM, output voltage increases if: A) Load decreases B) Load increases C) L increases D) fs decreases

From DCM gain: Vo ∝ R Load resistance increases → Vo increases Answer: B

---

🔹 Inverters

Q5. Single-phase square inverter Vdc = 200 V Fundamental RMS? A) 90 V B) 127 V C) 180 V D) 200 V

V1(rms) = (4Vdc)/(π√2) = (800)/(3.14×1.414) ≈ 180 V Answer: C

---

🔹 Controlled Rectifier

Q6. Single-phase full converter Vm = 325 V α = 60° Vo equals? A) 103 V B) 207 V C) 150 V D) 0

Vo = (2Vm/π)cosα = (650/3.14)(0.5) ≈ 103 V Answer: A

---

🔹 Stability

Q7. Buck converter transfer function order? A) 1 B) 2 C) 3 D) 4

Second order due to LC Answer: B

--- Q8. Natural frequency for L=200µH, C=100µF A) 7070 rad/s B) 5000 rad/s C) 10000 rad/s D) 15000 rad/s

ω₀ = 1/√(LC) = 1/√(200×10⁻⁶ × 100×10⁻⁶) = 1/√(2×10⁻⁸) ≈ 7070 rad/s Answer: A

---

🔹 Mixed Concept

Q9. Increasing switching frequency results in: A) Larger filter size B) Smaller filter size C) Higher ripple D) Lower efficiency

Higher fs → smaller L & C Answer: B

--- Q10. MOSFET is preferred in: A) High frequency B) High voltage (>5kV) C) Very high current industrial drives D) HVDC

MOSFET → high frequency switching Answer: A

---

Page 67 Advanced Takeaways

✔ DCM load effect ✔ Square inverter fundamentals ✔ Rectifier numerical ✔ Natural frequency calculation ✔ Switching frequency effect

Power Electronics Advanced MCQ Series – Shaktimatha Learning

Page 66 – 100 Very Tough MCQs (Part 1)

Level: GATE / PSU Advanced

🔹 Devices

Q1. IGBT is a combination of: A) BJT + MOSFET B) SCR + MOSFET C) MOSFET + Diode D) BJT + SCR

Answer: A

--- Q2. Latching current of SCR is: A) Minimum current to turn ON B) Minimum current to remain ON C) Maximum gate current D) Reverse current

Answer: A

---

🔹 Rectifiers

Q3. Single-phase full converter with RL load operates in inversion when: A) α < 90° B) α = 90° C) α > 90° D) α = 0°

Answer: C

--- Q4. Ripple factor of full-wave rectifier is approximately: A) 0.21 B) 0.48 C) 1.21 D) 0

Answer: B

---

🔹 DC-DC Converters

Q5. Boost converter duty cycle for doubling voltage is: A) 0.25 B) 0.5 C) 0.75 D) 1

Vo = Vin/(1−D) 2Vin = Vin/(1−D) D = 0.5 Answer: B

--- Q6. Buck-Boost converter polarity is: A) Same B) Opposite C) Zero D) AC

Answer: B

--- Q7. In DCM, gain depends on: A) Only D B) Only R C) D, R, L, fs D) Only L

Answer: C

---

🔹 Inverters

Q8. Fundamental RMS of square inverter output: A) Vdc B) 0.9Vdc C) (4Vdc)/(π√2) D) Vdc/2

Answer: C

--- Q9. THD decreases when: A) Switching frequency increases B) Switching frequency decreases C) Load increases D) Voltage increases

Answer: A

---

🔹 PWM & Control

Q10. Modulation index m > 1 causes: A) Linear region B) Under modulation C) Over modulation D) No output

Answer: C

---

🔹 Numerical Tough

Q11. Buck converter: Vin=30V, D=0.6, R=10Ω Find Io.

Vo = 18V Io = 18/10 = 1.8A Answer: 1.8A

--- Q12. Boost converter: Vin=24V, D=0.75 Vo = ?

Vo = 24/(1−0.75) = 24/0.25 = 96V Answer: 96V

--- Q13. Natural frequency of Buck: L=100µH, C=50µF

ω₀ = 1/√(LC) = 1/√(100×10⁻⁶ × 50×10⁻⁶) = 1/√(5×10⁻⁹) ≈ 14142 rad/s Answer: 14.14 krad/s

---

Page 66 Summary

✔ Devices fundamentals ✔ Rectifier inversion ✔ Boost & Buck calculations ✔ DCM vs CCM ✔ PWM modulation ✔ Stability basics

Power Electronics Very Tough MCQ Series – Shaktimatha Learning

Page 65 – Power Electronics Mega Question Bank (With Detailed Solutions)

Level: GATE / PSU Comprehensive Practice

🔹 Section 1 – Power Semiconductor Devices

Q1. Why is IGBT preferred over MOSFET at high voltage?

Answer:

IGBT has lower conduction loss at high voltage due to bipolar conduction. MOSFET has higher Rds(on) at high voltage ratings.

---

Q2. SCR Turn-off condition?

Answer:

Anode current must fall below holding current (Ih).

---

🔹 Section 2 – Controlled Rectifiers

Q3. Single-phase fully controlled rectifier average output voltage?

Solution:

Vo = (2Vm/π) cosα

---

Q4. If α = 60°, find output for Vm = 200 V.

Vo = (2×200/π) cos60 = (400/3.14)(0.5) ≈ 63.7 V

---

🔹 Section 3 – Choppers

Q5. Buck converter output voltage?

Vo = D × Vin

---

Q6. Vin = 50V, D=0.4 → Vo?

Vo = 0.4 × 50 = 20 V

---

Q7. Boost converter voltage gain?

Vo/Vin = 1/(1−D)

---

🔹 Section 4 – DC-DC Converters

Q8. Buck-Boost gain (CCM)?

Vo/Vin = −D/(1−D)

---

Q9. DCM gain depends on?

Duty cycle, Load resistance, Inductance, Switching frequency.

---

🔹 Section 5 – Inverters

Q10. Output RMS of square wave inverter?

Vrms = Vdc

---

Q11. Fundamental RMS value?

V1(rms) = (4Vdc)/(π√2)

---

🔹 Section 6 – PWM

Q12. What happens when modulation index m > 1?

Overmodulation occurs. Waveform becomes non-sinusoidal.

---

🔹 Section 7 – Numerical Advanced

Q13. Buck converter:

Vin = 24V D = 0.5 R = 12Ω Find Io.

Vo = 0.5×24 = 12V Io = 12/12 = 1A

---

Q14. Boost converter:

Vin = 20V D = 0.6 Find Vo.

Vo = 20/(1−0.6) = 20/0.4 = 50V

---

Q15. Inductor ripple in buck:

Vin=30V, D=0.4, L=100µH, fs=50kHz

ΔIL = VinD/(Lfs) = 30×0.4/(100×10⁻⁶×50000) = 12/5 = 2.4A

---

🔹 Section 8 – Stability & Control

Q16. Buck converter order?

Second order system (LC filter).

---

Q17. Natural frequency?

ω₀ = 1/√(LC)

---

Q18. ESR effect?

Introduces zero → improves phase margin.

---

Final Power Electronics Master Summary

✔ SCR → Line commutation ✔ Buck → Vo = DVin ✔ Boost → Gain = 1/(1−D) ✔ Buck-Boost → Inverting ✔ DCM gain depends on R, L, fs ✔ Inverter fundamental important ✔ Control ensures stability

Power Electronics Mega Revision – Shaktimatha Learning

Page 64 – PWM Control & Small-Signal Modeling (Introduction)

Subject: Power Electronics + Control Systems
Level: GATE / PSU Conceptual

🔹 1️⃣ Why Control is Needed?

DC-DC converters are nonlinear systems. To maintain constant output voltage despite load or input variation, we use feedback control.

Regulate output voltage
Improve stability
Reduce steady-state error
Improve transient response

🔹 2️⃣ Pulse Width Modulation (PWM)

PWM controls output voltage by varying duty cycle (D).

Principle:

Compare control voltage with triangular carrier
When Vcontrol > Vtri → Switch ON
Duty cycle ∝ Control voltage

Output Voltage ∝ Duty Cycle

🔹 3️⃣ Feedback Control Block Diagram

Reference voltage (Vref)
Error amplifier
PWM generator
Power stage
Output feedback

Closed Loop = Stable + Regulated Output

🔹 4️⃣ Why Small-Signal Modeling?

Converters are nonlinear (switching systems). We linearize around operating point to analyze stability.

Idea:

Total variable = DC steady-state + small perturbation Example: D = D + d~ Vo = Vo + v~

🔹 5️⃣ Linearized Control-to-Output Transfer Function

For Buck Converter (CCM):

Gvd(s) = Vo(s) / d(s) = Vin / (1 + s(RC) + s²(LC))

Key Observations:

Second order system
Has double pole
ESR introduces zero

🔹 6️⃣ Important Frequency Concepts

Natural Frequency:

ω₀ = 1 / √(LC)

Quality Factor:

Q = R √(C/L)

Zero due to ESR:

ωz = 1 / (RESR × C)

🔹 7️⃣ Stability Design (Very Important)

Use Type I, Type II, Type III compensator
Ensure phase margin > 45°
Ensure gain margin adequate

GATE often asks:
✔ Location of poles
✔ Effect of ESR zero
✔ Stability conditions

🔥 Exam Memory Capsule

✔ PWM controls duty cycle ✔ Small-signal model = linearized model ✔ Buck converter → 2nd order system ✔ ESR introduces zero ✔ Control ensures voltage regulation

Power Electronics Control Series – Shaktimatha Learning

Page 63 – Ultra Hard Mixed DC-DC Numerical Test

Subject: Power Electronics
Level: GATE / PSU Advanced

🔹 Problem 1 – Identify Mode + Output Voltage

Buck-Boost converter: Vin = 15 V D = 0.5 L = 50 μH fs = 40 kHz R = 5 Ω Determine:
1) CCM or DCM
2) Output voltage

Step 1 – Find Lcritical

Lcritical = R(1−D)² / (2fs) = 5(0.5)² / (2×40000) = 5(0.25) / 80000 = 1.25 / 80000 = 15.6 μH

Given L = 50 μH > Lcritical → CCM

Step 2 – Output Voltage

Vo/Vin = −D/(1−D) = −0.5/0.5 = −1 Vo = −15 V

Final Answer: CCM, Vo = −15 V

🔹 Problem 2 – Boost Converter Ripple

Vin = 20 V D = 0.6 L = 200 μH fs = 25 kHz Find inductor ripple current.

ΔIL = Vin D / (L fs) = 20×0.6 / (200×10⁻⁶ × 25000) = 12 / 5 = 2.4 A

Answer: 2.4 A

🔹 Problem 3 – SEPIC Duty Cycle

Vin varies 10–20 V Vo = 15 V Find duty cycle range.

Vo/Vin = D/(1−D) Case 1: Vin = 10 15/10 = 1.5 1.5 = D/(1−D) D = 0.6 Case 2: Vin = 20 15/20 = 0.75 0.75 = D/(1−D) D = 0.43

Duty cycle range: 0.43 – 0.6

🔹 Problem 4 – Ćuk Converter Power

Vin = 12 V D = 0.5 R = 8 Ω Find output power.

Vo/Vin = −D/(1−D) = −0.5/0.5 = −1 Vo = −12 V Io = 12/8 = 1.5 A P = Vo × Io = 12 × 1.5 = 18 W

Answer: 18 W

🔹 Problem 5 – DCM Output

Vin = 24 V D = 0.4 R = 20 Ω L = 100 μH fs = 50 kHz Find Vo (DCM).

Vo/Vin = − (D² R) / (2Lfs) = − (0.16 × 20) / (2×100×10⁻⁶ × 50000) = − (3.2) / (10) = −0.32 Vo = −0.32 × 24 = −7.68 V

Final Answer: −7.68 V

Master Concept Summary

✔ CCM → Gain depends only on D ✔ DCM → Gain depends on R, L, fs ✔ Always check Lcritical ✔ SEPIC = Non-inverting ✔ Ćuk = Low ripple ✔ Buck-Boost = Inverting

Ultra Hard DC-DC Series – Shaktimatha Learning

Page 62 – Buck-Boost Converter in DCM (Complete Derivation)

Subject: Power Electronics
Level: GATE / PSU Conceptual + Numerical

🔹 1️⃣ What is DCM?

DCM occurs when inductor current falls to zero before next switching cycle.
✔ Happens at light load
✔ Smaller inductance
✔ High switching frequency

🔹 2️⃣ DCM Operation (Three Intervals)

Interval 1 (0 → DT): Switch ON, inductor charges
Interval 2 (DT → (D+δ)T): Diode conducts, inductor discharges
Interval 3: Inductor current = 0

🔹 3️⃣ Inductor Current Peak

ΔIL = (Vin × D) / (L × fs)

Since current starts from zero:

Ipeak = (Vin × D) / (L × fs)

🔹 4️⃣ Average Output Current

Output current equals average diode current.

Io = (1/2) × Ipeak × δ

Where δ = diode conduction fraction.

🔹 5️⃣ Final DCM Voltage Gain (Important Result)

After solving energy balance:

Vo / Vin = − (D² × R) / (2Lfs)

🔥 VERY IMPORTANT: In DCM, voltage gain depends on: ✔ Duty cycle ✔ Load resistance ✔ Inductance ✔ Switching frequency Unlike CCM, gain is NOT only function of D.

🔹 6️⃣ Numerical Example

Vin = 20 V D = 0.4 L = 100 μH fs = 50 kHz R = 10 Ω Find output voltage (DCM).

Vo/Vin = − (D² R) / (2Lfs) = − (0.16 × 10) / (2 × 100×10⁻⁶ × 50000) = − (1.6) / (10) = −0.16

Vo = −0.16 × 20 = −3.2 V

Final Answer: −3.2 V

🔹 7️⃣ Critical Condition (Boundary CCM/DCM)

Boundary inductance:

Lcritical = R(1−D)² / (2fs)

If L < Lcritical → DCM If L > Lcritical → CCM

CCM vs DCM Comparison

Feature	CCM	DCM
Inductor Current	Never zero	Falls to zero
Voltage Gain	−D/(1−D)	Depends on R, L, fs
Control	Simpler	More complex

GATE Strategy Tip

If question gives L, R, fs → Think DCM possibility.
If only D given → Usually CCM.

Advanced DC-DC Control Series – Shaktimatha Learning

Page 61 – SEPIC Converter (Design Example + Component Selection)

Subject: Power Electronics
Level: GATE / PSU + Practical Design

🔹 1️⃣ What is SEPIC?

SEPIC = Single-Ended Primary Inductor Converter ✔ Non-inverting output ✔ Can step-up or step-down ✔ Continuous input current ✔ Widely used in battery-powered systems

Voltage Gain (CCM):

Vo / Vin = D / (1 − D)

🔹 2️⃣ Design Problem

Design a SEPIC converter with:
Vin = 12 V
Required Vo = 24 V
Load Power = 48 W
Switching Frequency fs = 50 kHz
Allow ripple current = 30% of average current

🔹 3️⃣ Step 1 – Duty Cycle

Vo/Vin = D/(1−D) 24/12 = D/(1−D) 2 = D/(1−D) 2(1−D) = D 2 − 2D = D 2 = 3D D = 0.667

🔹 4️⃣ Step 2 – Output Current

Io = P / Vo = 48 / 24 = 2 A

🔹 5️⃣ Step 3 – Inductor Design

Average input current:

Pin ≈ Pout Iin = P / Vin = 48 / 12 = 4 A

Allow 30% ripple:

ΔIL = 0.3 × 4 = 1.2 A

Inductor formula:

L = (Vin × D) / (ΔIL × fs)

L = (12 × 0.667) / (1.2 × 50000) = 8 / 60000 = 133 μH

Choose: L1 = L2 ≈ 150 μH (standard value)

🔹 6️⃣ Step 4 – Coupling Capacitor (C1)

Approximation formula:

C1 ≥ Io × D / (ΔVc × fs)

Assume allowed ripple ΔVc = 1 V

C1 = (2 × 0.667) / (1 × 50000) = 1.334 / 50000 = 26.6 μF

Select: 33 μF

🔹 7️⃣ Step 5 – Output Capacitor

Co ≥ Io × D / (ΔVo × fs)

Assume ripple 0.5 V

Co = (2 × 0.667) / (0.5 × 50000) = 1.334 / 25000 = 53 μF

Select: 68 μF

🔹 8️⃣ Final Design Summary

Parameter	Value
Duty Cycle	0.667
Inductors	150 μH
C1	33 μF
Co	68 μF

Exam Memory Capsule

✔ SEPIC gain = D/(1−D) ✔ Non-inverting output ✔ Two inductors ✔ Design based on ripple percentage ✔ Very common in battery & automotive systems

Advanced DC-DC Design Series – Shaktimatha Learning

Page 60 – Ćuk Converter (Detailed Derivation + Numericals)

Subject: Power Electronics
Level: GATE / PSU Advanced

🔹 1️⃣ Circuit Overview

Ćuk converter uses:
✔ Two inductors (L1, L2)
✔ Energy transfer capacitor (C1)
✔ Output capacitor (C2)
✔ Switch + Diode

Special Feature:

Continuous input current
Continuous output current
Low ripple

🔹 2️⃣ Derivation of Voltage Gain (CCM)

Mode 1 (Switch ON):

L1 charges from source
Diode OFF
Capacitor C1 discharges to L2

Mode 2 (Switch OFF):

L1 transfers energy to C1
Diode ON
L2 supplies load

Apply Volt-Second Balance on L1:

Vin × D + (Vin − Vc1)(1 − D) = 0

Apply Volt-Second Balance on L2:

(−Vc1 − Vo)D + (−Vo)(1 − D) = 0

Solving both equations gives:

Vo / Vin = − D / (1 − D)

Important: Same gain as Buck-Boost but with smoother current.

🔹 3️⃣ Numerical Problem 1 – Output Voltage

Vin = 20 V D = 0.6 Find output voltage.

Vo = − (0.6 / 0.4) × 20 = −1.5 × 20 = −30 V

Answer: −30 V

🔹 4️⃣ Numerical Problem 2 – Inductor Current

Vin = 24 V Vo = −48 V R = 12 Ω Find output current and average L2 current.

Io = 48 / 12 = 4 A |Vo/Vin| = 48/24 = 2 2 = D/(1−D) D = 0.667 IL2(avg) = Io = 4 A

Note: In Ćuk converter, output inductor current equals load current.

🔹 5️⃣ Numerical Problem 3 – Ripple Current

Vin = 30 V D = 0.4 L1 = 150 μH fs = 40 kHz Find ripple current in L1.

ΔIL1 = (Vin × D) / (L1 × fs) = (30 × 0.4) / (150×10⁻⁶ × 40000) = 12 / 6 = 2 A

Answer: 2 A

🔹 6️⃣ Critical Inductance Condition

To maintain CCM: L > (R (1−D)²) / (2 fs)

Same expression form as buck-boost.

Exam Comparison – Buck-Boost vs Ćuk

Parameter	Buck-Boost	Ćuk
Inductors	1	2
Ripple	Medium	Low
Gain	−D/(1−D)	−D/(1−D)
Exam Weight	High	Moderate-High

Advanced Converter Series – Shaktimatha Learning

Page 59 – Buck-Boost Converter Numerical Problems (CCM)

Subject: Power Electronics
Level: GATE / PSU Numerical Practice

🔹 Problem 1 – Output Voltage Calculation

A buck-boost converter operates in CCM with:
Vin = 24 V
Duty cycle D = 0.6
Find output voltage.

Vo / Vin = − D / (1 − D)

Vo = − (0.6 / 0.4) × 24 = −1.5 × 24 = −36 V

Final Answer: −36 V

🔹 Problem 2 – Duty Cycle Required

Vin = 48 V Required Vo = −24 V Find duty cycle.

|Vo/Vin| = D / (1 − D) 24/48 = D/(1−D) 0.5 = D/(1−D) 0.5(1−D) = D 0.5 − 0.5D = D 0.5 = 1.5D D = 0.333

Final Answer: D = 0.333 (33.3%)

🔹 Problem 3 – Inductor Current

Vin = 20 V Vo = −40 V Load resistance R = 10 Ω Find output current and average inductor current.

Io = |Vo| / R = 40 / 10 = 4 A For buck-boost in CCM: I_L(avg) = Io / (1 − D) First find D: |Vo/Vin| = D/(1−D) 40/20 = D/(1−D) 2 = D/(1−D) 2(1−D) = D 2 − 2D = D 2 = 3D D = 0.667 Now, IL(avg) = 4 / (1 − 0.667) = 4 / 0.333 ≈ 12 A

Final Answer: Io = 4 A IL(avg) ≈ 12 A

🔹 Problem 4 – Critical Inductance

Vin = 30 V Vo = −60 V R = 12 Ω Switching frequency fs = 25 kHz Find critical inductance.

For buck-boost: L_critical = (R (1−D)²) / (2 fs)

First find D: |Vo/Vin| = 60/30 = 2 2 = D/(1−D) D = 0.667 Now, L = (12 × (0.333)²) / (2 × 25000) = (12 × 0.111) / 50000 = 1.332 / 50000 = 26.6 μH

Final Answer: 26.6 μH

🔹 Problem 5 – Ripple Current

Vin = 24 V D = 0.5 L = 200 μH fs = 50 kHz Find inductor ripple current.

ΔIL = (Vin × D) / (L × fs) = (24 × 0.5) / (200×10⁻⁶ × 50000) = 12 / 10 = 1.2 A

Final Answer: 1.2 A

Exam Memory Capsule

✔ Vo/Vin = −D/(1−D) ✔ Output is negative ✔ IL(avg) = Io/(1−D) ✔ Lcritical = R(1−D)² / (2fs) ✔ ΔIL = VinD / (Lfs)

Buck-Boost Numerical Series – Shaktimatha Learning

Page 58 – Advanced DC-DC Converters (Buck-Boost, Ćuk, SEPIC)

Subject: Power Electronics
Level: GATE / PSU Advanced

🔹 1️⃣ Inverting Buck-Boost Converter

Output voltage is inverted and can be higher or lower than input.

Voltage Gain (CCM):

Vo / Vin = − D / (1 − D)

D → Duty cycle
Output polarity → Negative

Key Points:

Simple structure
Single inductor
Higher ripple compared to Cuk

🔹 2️⃣ Ćuk Converter

Uses capacitor for energy transfer and two inductors for smooth current.

Voltage Gain (CCM):

Vo / Vin = − D / (1 − D)

Special Feature:

Continuous input current
Continuous output current
Low ripple

Applications:

Precision power supplies
Low ripple DC systems

🔹 3️⃣ SEPIC Converter

Single-Ended Primary Inductor Converter Non-inverting output, can step up or step down.

Voltage Gain (CCM):

Vo / Vin = D / (1 − D)

Features:

Non-inverting output
Two inductors
Used in battery systems

🔹 4️⃣ Comparison Table

Converter	Polarity	Voltage Gain	Ripple
Buck-Boost	Inverting	−D/(1−D)	Medium
Ćuk	Inverting	−D/(1−D)	Low
SEPIC	Non-Inverting	D/(1−D)	Low

Exam Memory Capsule

✔ Buck-Boost → Simple, inverting ✔ Ćuk → Smooth current, low ripple ✔ SEPIC → Non-inverting ✔ Gain depends only on Duty Cycle ✔ CCM analysis important for GATE

Advanced DC-DC Converter Series – Shaktimatha Learning

Page 57 – Ultra Hard Mixed Test (Multilevel + PWM)

Subject: Power Electronics
Level: GATE / PSU Ultra Advanced

🔹 Q1.

A CHB inverter has 4 H-bridges per phase. Find number of output levels.

Levels = 2n + 1 = 2(4) + 1 = 9

Answer: 9 Levels

🔹 Q2.

For a 5-level NPC inverter, find number of clamping diodes per phase.

Diodes = (m−1)(m−2) = (5−1)(5−2) = 4×3 = 12

Answer: 12 diodes

🔹 Q3.

For a 7-level FC inverter, find number of flying capacitors per phase.

Capacitors = (m−1)(m−2)/2 = (7−1)(7−2)/2 = (6×5)/2 = 15

Answer: 15 capacitors

🔹 Q4.

A 3-level NPC inverter operates with Vdc = 900 V. Find switch voltage stress.

Stress = Vdc/(m−1) = 900/(3−1) = 450 V

Answer: 450 V

🔹 Q5.

In Phase-Shifted PWM for 7-level CHB, find carrier phase shift.

Number of carriers = m−1 = 6 Phase shift = 360°/6 = 60°

Answer: 60°

🔹 Q6.

Increasing number of levels mainly reduces: A) Switching loss B) Voltage rating C) THD D) DC source

Answer: C

🔹 Q7.

Which inverter requires multiple isolated DC sources? A) NPC B) CHB C) FC D) 2-Level

Answer: B (CHB)

🔹 Q8.

Which PWM technique is best for CHB inverter? A) Level-shifted B) Phase-shifted C) Sinusoidal only D) Random PWM

Answer: B

🔹 Q9.

For 9-level NPC inverter, find switch stress if Vdc = 1200 V.

Stress = 1200/(9−1) = 1200/8 = 150 V

Answer: 150 V

🔹 Q10.

More flying capacitors lead to: A) Easier balancing B) Complex control C) Lower switching frequency D) Lower voltage stress

Answer: B

Ultra Memory Capsule

✔ CHB → Multiple DC sources ✔ NPC → Many diodes ✔ FC → Many capacitors ✔ Stress = Vdc/(m−1) ✔ Levels = 2n + 1 ✔ PS-PWM shift = 360°/(m−1)

Ultra Advanced Mixed Test – Shaktimatha Learning

Page 56 – PWM Techniques for Multilevel Inverters

Subject: Power Electronics
Level: GATE / PSU / Interview Advanced

🔹 1. Why PWM for Multilevel Inverters?

PWM is used to:

Control output voltage magnitude
Reduce THD
Improve waveform quality
Balance capacitor voltages

🔹 2. Types of PWM Techniques

1️⃣ Level-Shifted PWM (LS-PWM)

Used mainly in NPC and FC inverters. Multiple carrier signals are vertically shifted.

Types:

PD (Phase Disposition)
POD (Phase Opposition Disposition)
APOD (Alternate Phase Opposition Disposition)

2️⃣ Phase-Shifted PWM (PS-PWM)

Used mainly in Cascaded H-Bridge (CHB). Carrier signals are phase shifted by:

Phase shift = 360° / number of carriers

Example: For 5-level → 4 carriers Phase shift = 360° / 4 = 90°

3️⃣ Space Vector PWM (SVPWM)

Extension of conventional SVPWM to multilevel inverters. Provides better DC bus utilization and lower THD.

🔹 3. Comparison of PWM Methods

PWM Method	Used For	Complexity	THD
Level-Shifted PWM	NPC, FC	Medium	Low
Phase-Shifted PWM	CHB	Simple	Low
SVPWM	All Types	High	Very Low

🔹 4. Important GATE Concepts

✔ Phase shift in PS-PWM = 360° / carriers ✔ LS-PWM uses vertically shifted carriers ✔ SVPWM gives better DC bus utilization ✔ More levels → easier harmonic reduction ✔ Capacitor balancing important in FC

PWM Techniques Series – Shaktimatha Learning

Page 55 – Complete Comparison of Multilevel Inverters

Subject: Power Electronics
Level: GATE / PSU / Interview Revision

🔹 1. Overview

There are three major types of Multilevel Inverters:

Cascaded H-Bridge (CHB)
Neutral Point Clamped (NPC)
Flying Capacitor (FC)

🔹 2. Comparison Table

Parameter	CHB	NPC	Flying Capacitor
DC Source	Multiple Isolated	Single (Split)	Single Source
Clamping Diodes	Not Required	(m−1)(m−2)	Not Required
Flying Capacitors	Not Required	Not Required	(m−1)(m−2)/2
Switches per Phase	4n	2(m−1)	2(m−1)
Voltage Stress	Vdc	Vdc/(m−1)	Vdc/(m−1)
Control Complexity	Simple	Medium	High
Main Issue	Multiple DC supplies	Neutral balancing	Capacitor balancing
Best Application	Solar, Drives	HVDC, FACTS	Reactive power control

🔹 3. Quick Formula Summary

✔ CHB Levels = 2n + 1 ✔ NPC Diodes = (m−1)(m−2) ✔ FC Capacitors = (m−1)(m−2)/2 ✔ Switch stress (NPC & FC) = Vdc/(m−1) ✔ More levels → Lower THD

🔹 4. GATE Exam Trick

If question says:
• Multiple DC sources → CHB
• Many diodes → NPC
• Many capacitors → Flying Capacitor

Multilevel Inverter Comparison Series – Shaktimatha Learning

Page 54 – Flying Capacitor Multilevel Inverter

Subject: Power Electronics
Level: GATE / PSU / Interview

🔹 1. What is Flying Capacitor Inverter?

Flying Capacitor (FC) Multilevel Inverter uses capacitors instead of clamping diodes to generate intermediate voltage levels.

It is also called Capacitor-Clamped Multilevel Inverter.

🔹 2. Basic 3-Level FC Structure

4 switches per phase
Flying capacitor
Single DC source

Output Levels: +Vdc/2 0 −Vdc/2

🔹 3. Working Principle

Capacitors are charged to specific voltages and inserted in series with DC source to produce stepped output.

Voltage balancing is achieved by controlling switching sequence.

🔹 4. Number of Capacitors

Number of flying capacitors per phase = (m − 1)(m − 2) / 2

Where m = number of levels Example: For 3-level → (3−1)(3−2)/2 = 1 capacitor

🔹 5. Voltage Stress

Switch voltage stress = Vdc / (m − 1)

Same as NPC inverter.

🔹 6. Advantages

No clamping diodes required
Better redundancy in switching states
Good for reactive power control
Reduced voltage stress

🔹 7. Disadvantages

Large number of capacitors
Complex voltage balancing
Higher cost
Bulky structure

🔹 8. Comparison Insight

NPC → Many diodes
CHB → Many isolated DC sources
FC → Many capacitors

🔥 Exam Important Formulas

✔ Flying Capacitors = (m − 1)(m − 2)/2 ✔ Switch stress = Vdc/(m − 1) ✔ Output levels = m ✔ Complex voltage balancing control

Multilevel Inverter Series – Shaktimatha Learning

Page 53 – Numerical Problems (NPC Multilevel Inverter)

Subject: Power Electronics
Level: GATE / PSU Advanced Numericals

🔹 Problem 1 – Number of Clamping Diodes

Find the number of clamping diodes per phase for a 4-level NPC inverter.

Formula: Diodes = (m − 1)(m − 2)

m = 4 Diodes = (4 − 1)(4 − 2) = 3 × 2 = 6 diodes per phase

Final Answer: 6 diodes per phase

🔹 Problem 2 – Switch Voltage Stress

A 3-level NPC inverter operates with Vdc = 800 V. Find maximum voltage stress across each switch.

Switch stress = Vdc / (m − 1) For 3-level: = 800 / (3 − 1) = 800 / 2 = 400 V

Final Answer: 400 V

🔹 Problem 3 – Output Voltage Levels

For a 3-level NPC inverter with Vdc = 600 V, list output levels.

Output levels: +Vdc/2 = +300 V 0 −300 V

Answer: +300 V, 0, −300 V

🔹 Problem 4 – Total Switch Count

Find total number of switches in a 3-phase 3-level NPC inverter.

Switches per phase = 4

Total = 3 × 4 = 12 switches

Final Answer: 12 switches

🔹 Problem 5 – Diodes in 3-Phase System

For 3-phase 4-level NPC inverter, find total clamping diodes.

Per phase = 6 diodes Total = 3 × 6 = 18 diodes

Final Answer: 18 diodes

🔹 Problem 6 – Compare Voltage Stress

Compare switch stress in: 1) 2-level inverter 2) 3-level NPC inverter Assume Vdc = 900 V.

2-level → stress = 900 V 3-level NPC → stress = 900 / 2 = 450 V

Conclusion: NPC reduces stress by 50%

🔥 Exam Memory Section

✔ Diodes = (m − 1)(m − 2) ✔ Switch stress = Vdc / (m − 1) ✔ 3-Level → 4 switches per phase ✔ NPC reduces voltage stress ✔ Balancing of neutral point required

NPC Numerical Series – Shaktimatha Learning

Page 52 – NPC (Neutral Point Clamped) Multilevel Inverter

Subject: Power Electronics
Level: GATE / PSU / Interview

🔹 1. What is NPC Inverter?

NPC (Neutral Point Clamped) inverter uses clamping diodes to divide the DC bus voltage into multiple levels.

It is also called Diode-Clamped Multilevel Inverter.

🔹 2. Basic 3-Level NPC Structure

A 3-level NPC inverter has:

4 switches per phase
2 clamping diodes
Split DC capacitor (Vdc/2 + Vdc/2)

Output levels: +Vdc/2 0 −Vdc/2

🔹 3. Working Principle

The clamping diodes connect the output to the neutral point, limiting voltage stress on switches.

Switch voltage stress = Vdc / (number of levels − 1)

For 3-level: Switch stress = Vdc / 2

🔹 4. Number of Diodes Formula

Number of clamping diodes per phase = (m − 1)(m − 2)

Where: m = number of levels Example: For 3-level → (3−1)(3−2) = 2 diodes

🔹 5. Advantages

Reduced voltage stress
Better harmonic performance
High voltage applications
No isolated DC sources required

🔹 6. Disadvantages

Large number of diodes for higher levels
Neutral point voltage balancing issue
Complex control for higher levels

🔹 7. Comparison with CHB

NPC → Single DC source (split capacitor)
CHB → Multiple isolated DC sources
NPC → More diodes
CHB → More DC supplies

Important Exam Points

✔ 3-Level NPC → 4 switches + 2 diodes ✔ Output: +Vdc/2, 0, −Vdc/2 ✔ Diodes = (m−1)(m−2) ✔ Switch stress reduced ✔ Neutral balancing required

Multilevel Inverter Series – Shaktimatha Learning

Page 51 – Numerical Problems (5-Level CHB Inverter)

Subject: Power Electronics
Level: GATE / PSU Advanced Numericals

🔹 Problem 1 – Number of Levels

A cascaded H-bridge inverter uses 3 identical H-bridge cells per phase. Find number of output voltage levels.

Formula: Levels = 2n + 1

n = 3 Levels = 2(3) + 1 = 7

Final Answer: 7 levels

🔹 Problem 2 – Maximum Output Voltage

A 5-level CHB inverter uses two DC sources of 200 V each. Find maximum output voltage.

Maximum output = +2Vdc = 200 + 200 = 400 V

Final Answer: 400 V

🔹 Problem 3 – Voltage Steps

For a 5-level inverter with Vdc = 250 V, list all output voltage levels.

+2Vdc = +500 V +Vdc = +250 V 0 −250 V −500 V

Answer: +500, +250, 0, −250, −500 V

🔹 Problem 4 – Total Number of Switches

Each H-bridge uses 4 switches. For a 5-level CHB inverter (2 H-bridges per phase), find total switches per phase.

Switches per H-bridge = 4 Total = 2 × 4 = 8 switches per phase

Final Answer: 8 switches per phase

🔹 Problem 5 – 3-Phase System Switch Count

For a 3-phase 5-level CHB inverter, find total number of switches.

Per phase = 8 switches 3 phases → 3 × 8 = 24 switches

Final Answer: 24 switches

🔹 Problem 6 – THD Concept

If number of levels increases from 5 to 7, what happens to THD?

More levels → waveform closer to sine → THD decreases.

🔹 Problem 7 – Required DC Sources

A 9-level CHB inverter is required. Find number of H-bridge cells per phase.

Levels = 2n + 1

9 = 2n + 1 2n = 8 n = 4

Final Answer: 4 H-bridges per phase

Exam Memory Section

✔ Levels = 2n + 1 ✔ Switches per phase = 4n ✔ More levels → Lower THD ✔ 5-level → 2 DC sources ✔ 7-level → 3 DC sources

Multilevel Inverter Numerical Series – Shaktimatha Learning

Page 50 – 5-Level Cascaded H-Bridge Inverter (Detailed Operation)

Subject: Power Electronics
Level: GATE / PSU / Interview Advanced

🔹 1. Basic Concept

A 5-level inverter can be built using 2 H-bridge cells connected in series.

Using formula: Levels = 2n + 1 n = 2 → Levels = 5

🔹 2. Output Voltage Levels

Possible output voltages: +2Vdc +Vdc 0 −Vdc −2Vdc

🔹 3. Switching Combinations

Each H-bridge can produce:

+Vdc
0
−Vdc

By combining two bridges: (+Vdc + +Vdc) = +2Vdc (+Vdc + 0) = +Vdc (+Vdc + −Vdc) = 0 (0 + −Vdc) = −Vdc (−Vdc + −Vdc) = −2Vdc

🔹 4. Advantages of 5-Level CHB

Better waveform quality
Reduced THD
Lower filter requirement
Suitable for medium voltage drives

🔹 5. Harmonic Reduction

More levels → waveform closer to sine → Lower THD → smaller filter → better efficiency.

🔹 6. Applications

Renewable energy systems
Solar inverters
HVDC systems
FACTS devices
Medium voltage motor drives

Important Exam Points

✔ Levels = 2n + 1 ✔ 2 H-bridges → 5 levels ✔ THD decreases with more levels ✔ Requires isolated DC sources ✔ High voltage capability

Multilevel Inverter Series – Shaktimatha Learning

Page 49 – Multilevel Inverter (MLI) – Introduction

Subject: Power Electronics
Level: GATE / PSU / Interview

🔹 1. What is a Multilevel Inverter?

A multilevel inverter produces output voltage with multiple discrete levels instead of only two levels (+Vdc and −Vdc).

Instead of square waveform → staircase waveform → closer to sine wave.

🔹 2. Why Multilevel Inverters?

Lower harmonic distortion (THD)
Reduced switching losses
Lower dv/dt stress
Better output waveform quality
Suitable for high voltage applications

🔹 3. Types of Multilevel Inverters

1️⃣ Diode Clamped (Neutral Point Clamped - NPC)

Uses clamping diodes to achieve multiple voltage levels.

2️⃣ Flying Capacitor (Capacitor Clamped)

Uses capacitors to generate intermediate voltage levels.

3️⃣ Cascaded H-Bridge (CHB)

Uses multiple H-bridge cells with isolated DC sources.

🔹 4. Number of Output Levels

For Cascaded H-Bridge: Number of levels = 2n + 1 Where n = number of H-bridge cells

Example: n = 2 → Levels = 5 n = 3 → Levels = 7

🔹 5. Advantages

Low THD
Reduced filter requirement
Suitable for HVDC & FACTS
High power applications

🔹 6. Disadvantages

More components
Complex control
Voltage balancing issues

Exam Important Formula

CHB Levels = 2n + 1 NPC Diodes = (m − 1)(m − 2) Switch count increases with level

Multilevel Inverter Series – Shaktimatha Learning

Page 48 – Ultra Hard Multi-Step Problems

Subject: Power Electronics
Level: GATE / PSU Ultra Advanced

🔹 Problem 1 – Combined SPWM + Frequency + Voltage

A 3-phase inverter has Vdc = 750 V. Modulation index mₐ = 0.85. Switching frequency = 12 kHz. Fundamental frequency = 50 Hz. Find: 1) Maximum line voltage 2) Switching period 3) Frequency ratio mf

Step 1: Line voltage (SPWM) VLL = 0.866 × mₐ × Vdc = 0.866 × 0.85 × 750 = 552 V

Step 2: Switching period Ts = 1 / fs = 1 / 12000 = 83.3 μs

Step 3: Frequency ratio mf = fs / f = 12000 / 50 = 240

Final Answers: VLL ≈ 552 V Ts ≈ 83 μs mf = 240

🔹 Problem 2 – SVPWM Sector + Switching Times

Vdc = 600 V Ts = 100 μs Reference voltage = 400 V Angle α = 35° Find sector and T₁, T₂ (approx).

Sector width = 60° 35° lies in Sector 1

T₁ = Ts (Vref/Vdc) sin(60° − α) T₂ = Ts (Vref/Vdc) sin(α)

Vref/Vdc = 400/600 = 0.667 T₁ ≈ 100 × 0.667 × sin(25°) ≈ 100 × 0.667 × 0.422 ≈ 28 μs T₂ ≈ 100 × 0.667 × sin(35°) ≈ 100 × 0.667 × 0.574 ≈ 38 μs

T₀ = 100 − (28 + 38) = 34 μs

Final: Sector 1, T₁ ≈ 28 μs, T₂ ≈ 38 μs, T₀ ≈ 34 μs

🔹 Problem 3 – Overmodulation Decision + THD Concept

Vdc = 650 V Required line voltage = 600 V Check if SPWM works.

SPWM max = 0.866 × 650 = 563 V Required = 600 V > 563 V → SPWM cannot achieve → Overmodulation needed → THD increases

Conclusion: Operates in overmodulation region.

🔹 Problem 4 – Multi-Concept Trap (Phase + Line)

Vdc = 500 V mₐ = 0.9 Find: 1) Phase voltage 2) Line voltage

Phase voltage Vphase = mₐ × Vdc / 2 = 0.9 × 500 / 2 = 225 V

Line voltage VLL = √3 × Vphase = 1.732 × 225 ≈ 390 V

Final: Vphase = 225 V, VLL ≈ 390 V

Ultra Exam Memory Zone

✔ SPWM → 0.866 Vdc ✔ SVPWM → Vdc ✔ mf = fs / f ✔ T₀ = Ts − (T₁ + T₂) ✔ Overmodulation → Higher THD ✔ Sector width = 60°

Ultra Advanced Practice Series – Shaktimatha Learning

Page 47 – Very Hard Numerical Problems

Subject: Power Electronics
Level: GATE / PSU Advanced Numericals

🔹 Problem 1 – SPWM Fundamental Voltage

A 3-phase inverter operates with Vdc = 700 V and modulation index mₐ = 0.9. Find maximum fundamental line voltage.

VLL = 0.866 × mₐ × Vdc

= 0.866 × 0.9 × 700
= 0.866 × 630
= 545.6 V

Final Answer: 546 V

🔹 Problem 2 – SVPWM Switching Times

Switching period Ts = 100 μs. If T₁ = 35 μs and T₂ = 25 μs, find zero vector time.

T₀ = Ts − (T₁ + T₂)

= 100 − (35 + 25)
= 100 − 60
= 40 μs

Final Answer: 40 μs

🔹 Problem 3 – Overmodulation Region

For Vdc = 600 V and required line voltage = 580 V, determine if SPWM can achieve this.

Max SPWM line voltage = 0.866 × 600 = 519.6 V
Required = 580 V > 519.6 V
Hence SPWM cannot achieve → Overmodulation required.

Conclusion: Overmodulation region

🔹 Problem 4 – Switching Frequency Calculation

If switching period Ts = 50 μs, find switching frequency.

fs = 1 / Ts
= 1 / (50 × 10⁻⁶)
= 20 kHz

Final Answer: 20 kHz

🔹 Problem 5 – Harmonic Reduction

Switching frequency increased from 5 kHz to 15 kHz. Comment on harmonic performance.

Higher switching frequency → Harmonics shift to higher frequency → Easier filtering → Lower THD.

🔹 Problem 6 – Sector Identification

Reference angle α = 275°. Identify sector.

Each sector = 60°
240°–300° = Sector 5
275° lies in Sector 5.

Answer: Sector 5

🔹 Problem 7 – Phase Voltage

For Vdc = 500 V and mₐ = 0.8, find fundamental phase voltage.

Vphase = mₐ × Vdc / 2

= 0.8 × 500 / 2
= 400 / 2
= 200 V

Final Answer: 200 V

🔹 Problem 8 – DC Bus Utilization Comparison

Vdc = 800 V. Compare SPWM and SVPWM maximum line voltages.

SPWM max = 0.866 × 800 = 692.8 V
SVPWM max = 800 V
Improvement ≈ 107.2 V

Exam Memory Points

✔ SPWM max = 0.866 Vdc
✔ SVPWM max = Vdc
✔ T₀ = Ts − (T₁ + T₂)
✔ fs = 1/Ts
✔ Sector width = 60°

Advanced Numerical Series – Shaktimatha Learning

Page 46 – Very Tough Mixed MCQ Test

Subject: Power Electronics
Level: GATE / PSU Advanced

Q1.

In SPWM, linear modulation region exists for: A) mₐ > 1 B) mₐ < 1 C) mₐ = 2 D) mₐ = 0

Answer: B

Q2.

Maximum line voltage in SVPWM equals: A) 0.866 Vdc B) 0.707 Vdc C) Vdc D) 1.2 Vdc

Answer: C

Q3.

Total active vectors in a 3-phase inverter: A) 8 B) 6 C) 4 D) 2

Answer: B

Q4.

If switching frequency = 10 kHz, switching period Ts equals: A) 0.1 ms B) 1 ms C) 10 ms D) 100 μs

Answer: D

Q5.

If Vdc = 500V, find max fundamental line voltage in SPWM.

VLL = 0.866 × 500 = 433 V

Answer: 433 V

Q6.

Number of sectors in SVPWM: A) 4 B) 6 C) 8 D) 12

Answer: B

Q7.

Shoot-through condition occurs when: A) Zero vectors applied B) Both switches of same leg ON C) Dead-time inserted D) Reference vector zero

Answer: B

Q8.

Improvement of SVPWM over SPWM is approximately: A) 5% B) 10% C) 15% D) 20%

Answer: C

Q9.

If α = 150°, the vector lies in: A) Sector 1 B) Sector 2 C) Sector 3 D) Sector 4

Answer: C

Q10.

In 120° conduction mode, number of conducting switches: A) 3 B) 2 C) 6 D) 1

Answer: B

Q11.

Vdc = 600V. SVPWM max line voltage equals:

Answer: 600 V

Q12.

Total switching states:

Answer: 8

Q13.

Fundamental phase voltage in SPWM:

Answer: mₐ × Vdc / 2

Q14.

Dead-time is introduced to:

Answer: Prevent shoot-through

Q15.

Switching frequency affects: A) Output frequency B) Harmonics C) DC link voltage D) Load power factor

Answer: B

Q16.

If mₐ = 1.2, operation is:

Answer: Overmodulation

Q17.

Zero vectors are:

Answer: (000) and (111)

Q18.

Ts = 100 μs. If T₁ + T₂ = 70 μs, find T₀:

Answer: 30 μs

Q19.

In 180° mode, each switch conducts for:

Answer: 180°

Q20.

Maximum theoretical DC utilization in SPWM:

Answer: 86.6%

Q21–25.

Sector angle width = 60°
Reference vector rotates at fundamental frequency
Carrier frequency >> fundamental frequency
THD reduces when switching frequency increases
SVPWM reduces harmonic distortion compared to SPWM

Exam Strategy Tip

✔ Memorize 0.866 Vdc (SPWM)
✔ SVPWM = Vdc
✔ 8 states → 6 active + 2 zero
✔ 6 sectors → 60° each
✔ T₀ = Ts − (T₁ + T₂)

Advanced Power Electronics Practice – Shaktimatha Learning

Page 45 – Multiple Questions with Explanation

Subject: Power Electronics
Level: GATE / PSU Concept + Numerical Practice

🔹 Q1. In SPWM, maximum fundamental line voltage is:

A) Vdc
B) 0.5 Vdc
C) 0.866 Vdc
D) 1.2 Vdc

Correct Answer: C) 0.866 Vdc

Explanation:
In SPWM, modulation index mₐ ≤ 1 in linear region. Maximum achievable line voltage = √3/2 × Vdc ≈ 0.866 Vdc.

🔹 Q2. SVPWM improves DC bus utilization by approximately:

A) 5%
B) 10%
C) 15%
D) 25%

Correct Answer: C) 15%

Explanation:
SPWM max = 0.866 Vdc
SVPWM max = Vdc
Improvement ≈ (1 − 0.866)/0.866 ≈ 15%.

🔹 Q3. A three-phase inverter has how many switching states?

A) 6
B) 8
C) 4
D) 12

Correct Answer: B) 8

Explanation:
3 legs → each leg has 2 states.
Total states = 2³ = 8.
6 active vectors + 2 zero vectors.

🔹 Q4. If α = 75°, the reference vector lies in:

A) Sector 1
B) Sector 2
C) Sector 3
D) Sector 4

Correct Answer: B) Sector 2

Explanation:
Each sector = 60°.
Sector 1 → 0°–60°
Sector 2 → 60°–120°
75° lies in Sector 2.

🔹 Q5. If Vdc = 600 V and mₐ = 0.8 (SPWM), find fundamental line voltage.

VLL = 0.866 × mₐ × Vdc

= 0.866 × 0.8 × 600
= 0.866 × 480
≈ 415.7 V

Final Answer: ≈ 416 V

🔹 Q6. Why must upper and lower switches of same leg never be ON together?

Correct Answer: Shoot-through fault.

Explanation:
It directly short-circuits the DC supply, causing large current and device damage. Dead-time is introduced to avoid this.

🔹 Q7. In 180° conduction mode, how many switches conduct simultaneously?

A) 1
B) 2
C) 3
D) 6

Correct Answer: C) 3

Explanation:
In 180° mode, each switch conducts for 180°.
At any instant, 3 switches are ON.

Quick Exam Reminder

✔ SPWM → 0.866 Vdc
✔ SVPWM → Vdc
✔ 6 sectors (60° each)
✔ 8 switching states
✔ Avoid shoot-through fault

Power Electronics Exam Series – Shaktimatha Learning

Labels

Saturday, 28 February 2026

GATE Electrical – Analog Electronics Complete Structured Course

🔹 Subject Importance in GATE

🔹 Complete Syllabus Coverage Plan

1️⃣ Diodes

2️⃣ BJT

3️⃣ MOSFET

4️⃣ Differential & Multistage Amplifiers

5️⃣ Feedback & Stability

6️⃣ Operational Amplifiers

7️⃣ Oscillators

🔹 Learning Strategy

Friday, 27 February 2026

GATE Electrical – Power Electronics Complete Mega Master Library (2026)

🔹 1️⃣ Power Diode & Uncontrolled Rectifiers

🔹 2️⃣ Controlled Rectifiers (SCR Based)

🔹 3️⃣ Fully Controlled Bridge & Dual Converters

🔹 4️⃣ Three Phase Converters

🔹 5️⃣ DC-DC Converters (Choppers)

🔹 6️⃣ Inverters & PWM

🔹 7️⃣ Multilevel Inverters

🔹 8️⃣ Mega Practice & Tests

POWER ELECTRONICS – PAGE 19

Fully Controlled Bridge – Inverter Mode

1️⃣ When Does Inverter Mode Occur?

2️⃣ Condition for Inverter Operation

3️⃣ Average Voltage

4️⃣ Power Flow Direction

🎯 GATE Important

Page 70 – Complete Power Electronics Formula Sheet

🔹 1️⃣ Controlled Rectifiers

🔹 2️⃣ DC-DC Converters (CCM)

🔹 3️⃣ DCM Gain (Buck-Boost)

🔹 4️⃣ Ripple Equations

🔹 5️⃣ Critical Inductance

🔹 6️⃣ Inverters

🔹 7️⃣ LC Filter & Control

🔹 8️⃣ Device Formulas

🔹 9️⃣ Efficiency

Final Exam Checklist

Page 70 – Full Length GATE Pattern Mock Test (Power Electronics)

🔹 Section A – 1 Mark MCQs (10 × 1 = 10 Marks)

🔹 Section B – 2 Marks Numerical (10 × 2 = 20 Marks)

🔹 Section C – 3 Marks Tough Problems (5 × 3 = 15 Marks)

🔹 Answer Key (Brief)

Mock Test Strategy

Page 69 – Numerical Marathon (Part 2 – Ultra Hard)

🔹 Problem 1 – Mode Identification + Output

🔹 Problem 2 – Boost Ripple & Power

🔹 Problem 3 – Rectifier Inversion

🔹 Problem 4 – Buck Control Frequency

🔹 Problem 5 – SEPIC Duty Range

🔹 Problem 6 – Inverter THD Concept

🔹 Problem 7 – Energy Stored

🔹 Problem 8 – MOSFET Loss

Ultra Hard Key Learning

Page 68 – Numerical Marathon (30 Hard Problems – Part 1)

🔹 Problem 1 – Buck Converter

🔹 Problem 2 – Boost Converter

🔹 Problem 3 – Buck-Boost

🔹 Problem 4 – Inductor Ripple

🔹 Problem 5 – Critical Inductance

🔹 Problem 6 – Rectifier

🔹 Problem 7 – Inverter Fundamental

🔹 Problem 8 – Natural Frequency

🔹 Problem 9 – Boost Duty

🔹 Problem 10 – DCM Output

Marathon Strategy

Page 67 – 100 Very Tough MCQs (Part 2 – Advanced Numericals)

🔹 DC-DC Converters

🔹 DCM Concept

🔹 Inverters

🔹 Controlled Rectifier

🔹 Stability

🔹 Mixed Concept

Page 67 Advanced Takeaways

Page 66 – 100 Very Tough MCQs (Part 1)

🔹 Devices

🔹 Rectifiers